A CMOS Implementation of a Neural Network Model.

We describe a CMOS VLSI chip with an architecture based on a connectionist model for neural networks. It consists of an array of 54 amplifiers and a coupling network where each amplifier can be programmed to source or sink current into the input line of every other amplifier. One of three coupling levels can be chosen between two amplifiers: an excitatory, an inhibitory or no coupling at all. The state of each amplifier is determined by analog current summing into its input line. The architecture of this chip is sufficiently general that several different collective computing circuits may be mapped into the chip simply by choosing appropriate connections in the coupling network. This chip has been developed to study the potential of neural network models working as associative memories for the use in signal processing and for pattern recognition in particular.