A Single-chip Digital Signaling Interface for the DSI Intraoffice Environment
15 February 1989
A monolithic analog/digital CMOS transceiver meeting the DS1 (1.544 Mb/s) intraoffice requirements is presented. The device contains a line driver that reduces chip power consumption to 115mW, about one third the power of existing devices. The transceiver, designed in a 1.75micron CMOS process, occupies 20mm sup 2 of area and operates from a 5V supply.