A symmetric submicron CMOS Technology.
01 January 1987
A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi sub 2 source/drains with sheet resistivities of 1. 5-2 Omega/square, n+ and p+ polysilicon/ TaSi sub 2 gate structures, Threshold voltages of 0.4 V and 1.5micron separation between active to tub-edge regions. Diode characteristics of the CoSi sub 2/n+ and CoSi sub 2/p+ are determined to be as good as non-silicided silicon junctions.