An Efficient Implementation of the LPC-10e Speech Coding Algorithm

The viability of a low-cost real-time narrow-band voice coder with good speech quality will be demonstrated. We describe a hardware implementation of the U.S. Government Enhanced Linear Predictive Coder, which compresses speech sampled ar 8kHz to 2400 bits per second. The hardware employs two fixed-point digital signal processors operating at 8.0 MHz mounted on a 200 cm2 board and consumes 2. 5 W. The voice-processor prototype, operating in dull-duplex mode with telephone handsets, will be available for demonstrations.