Area-Time Efficient Arithmetic Elements for VLSI Systems.

Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. This is because of constraints on floor- planning, inability to route the signals on metal only, large device sizes to achieve the needed drive capability, etc. Solutions that yield area- time efficient practical implementations of these arithmetic functions are described.