ASIC Implementations of Boundary-Scan and Built-In Self-Test (BIST)

Broad-based interest in the design for testability architecture known as boundary-scan has been promoted in recent years-in large part due to the activities of the Joint Test Action Group (JTAG) and the proposed boundary- scan standard they have promulgated. 

Boundary-scan provides a simple Test Access Port (TAP) and an associated protocol that make it possible to interface to built-in self-test (BIST) features within a chip, whether the chip in question is still in a wafer or is deeply embedded in a complex system. Testing the interconnection between chips on a printed wiring board (PWB) and sampling system signals during normal operation are also supported by the proposed boundary-scan standard.