Automation of BIST for Embedded RAM

This paper will discuss an automated implementation of built- in (BIST) for testing embedded, configureable RAMs in ASICs. Included are on-chip test vector generation as well as output data compression. This self-test feature provides vertical testability of RAMs not only for ASIC testing, but also for circuit board testing and system diagnostics. Details and examples of the BIST implementation and testing algorithm will be demonstrated.