Computation of Steady-State CMOS Latchup Characteristics

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. 

Making use of predictor-corrector continuation procedures and special initial- guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches.