Current testing procedure for deep submicron devices

This paper presents a test technique that employs two different supply voltages for the same IDDQ pattern. The results of the two measurements are subtracted in order to eliminate the inherent sub-threshold leakage. Summary of the experiment carried out on ``System on a Chip{''} (SOC) device build in 0.35 mu technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit IDDQ.