Delay Modeling for Wafer Scale Integration.

Wafer Scale Integration offers a number of potential advantages. However the penalty incurred is in the large amount of fault tolerance required in order to overcome the fabrication defects present. This fault tolerance is usually implemented through the provision of a reconfigurable interconnect to connect the fault free processors. Unless special processing techniques are used the reconfigurable interconnect can only be implemented using conventional process line switches. This of course introduces additional costs in terms of area and possible speed degradation. The subject of this memorandum is to investigate these costs in the framework of one particular reconfiguration scheme currently being fabricated.