Design objectives for ODL(TM)200 clock recovery and retiming module.

Development is now under way for a "one module" clock recovery and retiming circuit. This memorandum presents the design objectives for this code. The circuit is being designed as a general purpose clock recovery and retimer; one prime application is in the ODL(TM)200 system. The circuit consists of an MCBIC device and a SAW filter. The frequency of the SAW filter determines the specific bit rate, in the range 125 to 220 Mb/s. The module operates from a single supply voltage of either polarity; when used with a negative supply voltage it is 100K ECL compatible. When used in the ODL(TM) 200 system a clock can be recovered and the data retimed with only a 1 dB margin in receiver optical power sensitivity for a 10 E-9 B.E.R. The maximum total jitter on the output clock is less than 3 degrees R.M.S. The complete clock recovery and retiming circuit is packaged in a compact dual-in-line package.