Design of a programmable speech synthesizer.

This paper describes the single-chip implementation of a programmable speech synthesizer. It is based on the multi-pulsed linear predictive coding technique. The main features of the chip are a multiprocessor architecture, real time operation, micron/A- law coded PCM outputs and a flexible system interface. The chip is designed using 2.5 micron CMOS technology, operates with a single 10 MHz clock, and has a microcycle time of 200 nsec.