Design of Speed-Area Efficient Dual-Radix Arithmetic Units Via Decimal Carry Decomposition (NOT PUBLISHED)

In non-scientific computing such as data processing, decimal arithmetic is at least as important as binary arithmetic. As such, mainframes have contained a hardware decimal arithmetic unit form their early days, and modern general-purpose microprocessors have adapted this practice. In this paper, we report two decimal additional methods which fully utilize binary carry lookahead (CLA) addition without degrading the binary performance. In particular, use of these methods leads to design of integrated binary-decimal or dual-radix arithmetic units (AUs) which are highly speed-area efficient. We assume that binary-coded decimal (BCD) numbers are used for decimal arithmetic.