Design rule limitations due to hot carrier degradation of NMOS transistor under DC stress

The aim of this paper will be the assessment of design limitation due to degradation induced by hot-electrons on NMOS transistors under DC stress. Simulation will be used to assess the most relevant electrical parameter regarding the speed degradation of the product after 25 years AC. Based on DC stress results, an AC Safe Operating Area (SOA) can be defined by limiting the frequency, the fanout (which induces the rise time) and the operating voltage Vd. In order to qualify at Vdnom +10%, limitations have to be taken into account in the Design Rule Manual to achieve the product reliability target