Device Characterization for 0.75micron CMOS Technology.

As optimally designed process used for 0.75micron CMOS technology is described in this memorandum. This technology is designed for 5.5V maximum power supply voltage with 0.75micron minimum design rules and 0.6micron minimum effective N- and P-channel lengths. There are no chan-stop and Vt adjust masking levels used in this process. The transistors have been scaled to 0.55micron effective channel length without punch-through at Vds=5V. A separation of >/ 7micron N+ to P+ ensures latch- up immunity. Higher than 8V of snapback voltage is obtained on 0.6micron N-channel transistors. Hot carrier effects are suppressed by a modified LDD structure which provides greater than 10 years operating time to 10% degradation of Gm under worst-case D. C. conditions. A 140 ps stage delay is obtained on 51-stage CMOS ring oscillators which have close to nominal processing.