Diffusion of Co During Si Wafer Processing

The introduction of Co silicide into the process flow for Si integrated circuit manufacturing has necessitated a thorough understanding of the effec tof Co contamination on the electrical properties of both Si and SiO sub 2. In these experiments, Co was intentionally introduced into the Si by two methods; either 1MeV ion implantation at doses of 1x10 sup (11) or 1x10 sup (12) cm sup (-2) into the backside of the wafers, or by dipping into a Co solution. Quantox corona-oxide-semiconductor characterization and TXRF were used for analysis of metal diffusion during furnace het treatments. The Co diffused, at either 650C or 1000C for 30 minutes, from the back of the wafers to kill carrier recombination lifetime throughout the bulk Si. P/p+ epitaxial wafers gettered the Co, so that the near surface lifetime in epitaxial layers remained high even after contamination. There was no evidence of Co migration from the surface of wafers to adjoining wafers during furnace heat treatments, 900C, 30 minutes. Co diffused through 40A, 100A, or 1000A SiO sub 2 into bulk of Si. Co contamination introduced after oxide growth did not effect electrical properties of the oxides, i.e. Q sub (bd), D sub (it) or oxide tunneling voltages.