Efficient Test Architecture Based on Boundary Scan for Comprehensive System Test

In this talk, we present a comprehensive system test solution for complex systems based on IEEE 1149.1 standard based boundary scan technology. We propose to use the IEEE 1149.1 based test bus extended thru the backplane of a system to connect all circuit boards in a system. We use a test control processor (Boundary Scan Master chip from Agere Systems or Enhanced Test Bus Controller for TI) in a controller board of the system acting as a master device and use a slave processor (Addressable Scan Port from TI) in all other boards in rest of the system acts as a slave. This architecture is called multi-drop test architecture, which provides the access of all the circuit boards to the test control processor through the test bus.