Embedded Organic Low-kappa Structures for sub-0.18 micron CMOS VLSI MLM: Integration and Etching Issues

Interconnect delay is quickly becoming a significant factor limiting the clock-speed for advanced devices. To introduce low-kappa dielectrics without the complications introduced by Cu damascene processing requires that the low-kappa materials have excellent gap-fill capabilities to be compatible with Al metallization. In this paper, we describe how to create an embedded low-kappa layer that provides the primary benefit of low-kappa materials (capacitance reduction between metal lines) while retaining the oxide capping film to provide a stop layer for W CMP. We present favorable electrical data on 2-level metal wafers for vias chains as long as 8568 contacts.