Error characterization for a 2-D Discrete Cosine Transform implemented with planar rotations.

A new VLSI implementation of a 2-D Discrete Cosine Transform (DCT) using planar rotations has been carefully simulated at the logic level on real image data. The simulations exposed a regular error pattern in the resulting images which provoke a thorough analysis of the error induced by the DCT design. The two primary error-producing culprits were identified as coefficient approximation error, and truncation error. In this paper, the effects of both of these on the cumulative error are characterized theoretically and verified experimentally. Several ways to modify the DCT architecture to control and reduce the resulting error are then examined. We suggest that error estimation is a significant consideration in the architectural design of VLSI chips for fast signal processing transforms.