Exploiting Redundancy to Speedup Reconfiguration of an FPGA

Reconfigurable logic promises a flexible computing fabric well suited to the low cost, low power, high performance and fast time to market demanded of today's computing devices. This paper presents an analysis of what exactly occurs when a fine grain FPGA, specifically the Xilinx Virtex, is reconfigured, and proposes a tailorable approach to configuration architecture design trading off silicon area with reconfiguration time. 

It is shown that less than 3% of the bits contained in a typical Virtex reconfiguration bitstream are different to those already in the configuration memory, and a highly parallelisable compression technique is presented which achieves highly competitive results - 80% compression and better.