Fault Simulation in a Pipelined Multiprocessor System

This paper describes fault simulation algorithms for the MARS hardware accelerator designed and developed at the AT&T Bell Laboratories. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator. It is also easy to implement. These are perhaps the reasons for its popularity in recent commercial accelerators. The second algorithm, concurrent fault simulation, is found to have a performance that is nonlinear in the number of faults.