Fixed-Point Analysis and FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

A deep neural network (DNN) based equalizer is proposed to mitigate the intersymbol interference caused in the next generation high speed passive optical network (PON) link. The DNN based equalizer is shown to outperform the best known conventional equalizer, the maximum likelihood sequence estimator (MLSE) both in back-back and through fiber experiments. 

To reduce the hardware complexity of DNN based equalizer, we propose for the first time to use embedded parallelization within a DNN structure having multiple symbol outputs from one DNN. We further propose to use classification output stage with cross entropy cost to perform joint decision on multiple symbol outputs and demonstrated that the sensitivity gain of such scheme over regression output. 

To understand the complexity of hardware implementation, the fixed-point DNN based equalizers are developed and implemented in FPGA. The effect of fixed-point resolution is analyzed for the receiver sensitivity and hardware resource utilization in FPGA implementation. We show that a reduction of over 40 percent in LUTs (look up table) utilization is possible by reducing the DNN weight resolution from 8 bit to 4 bit while incurring a small penalty in receiver sensitivity.