Frequency enhancement of digital VLSI test systems.

While two expensive Japanese systems are capable of testing above 200 MB/s, most modern VLSI test systems operate below that frequency. This limitation is partially imposed by the frequency response of the driver and comparator circuits that interface with the Device-Under-Test (DUT). The bandwidth of the ECL wave formatting circuits preceding the drivers is also a determining factor. The purpose of this memo is to show how relatively low cost ( $7K per pin) test systems can be adapted to test up to 700 MB/s. The technique is to multiplex the outputs of test system drivers through the use of GaAs EX-OR gates external to the test system. The method assumes that the test system comparators have a much higher bandwidth than the drivers. In cases where the comparators have a restricted bandwidth, an external GaAs comparator can be used. The two main advantages of the proposed frequency enhancement technique are: (a) Purchase of more expensive systems can be avoided, thereby saving capital funds. (b) Testing can be performed at frequencies above those achievable by commercial VLSI test systems.