Gate Technology Issue for Silicon MOS Nanotransistors

This article has been prepared as an invited paper for Symposium J at the 1999 MRS fall meeting, Advanced Materials and Techniques for Nanolithography. It reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (~0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS an p-MOS type nanotransistors made using this process are discussed as are simulations of subthreshold currents for n-MOS transistors with physical gate lengths down to 26nm.