High performance salicide shallow junction CMOS devices for submicron VLSI application in Twin-Tub VI.

A 3.3 V CMOS technology with 0.6micron design rules in sixth generation of twin-tub CMOS (Twin-Tub VI) has been developed. The major features of the device in this technology are HIPOX twin-tub structures, N+/P+ dual-type poly gate, 125amgstrom thin gate oxide, shallow junctions, RTA activation, and thin TiSi sub 2 as source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latch-up immunity for 4.5micron N+ to P+ spacing, more than 6.0 V NMOSFET snapback breakdown voltage, good hot carrier aging properties, and undetectable dopant inter-lateral diffusion through TiSi sub 2 shunt layer of different type of poly. The transistors have been scaled to 0.45micron and 0.40micron effective channel length without punch-through at V sub ds = 3.6 V for NMOS and PMOS respectively. A 100 ps stage delay is obtained on 101-stage CMOS ring oscillator at operating voltage at 3.3 V.