Implementation of Low Frequency Finite State Machines using the Virtex SRL16 Primitive

This paper describes a novel technique for implementing finite state machines using the Xilinx Virtex SRL16 primitive. In the spirit of the term first introduced in (Keller et al., 2003), the technique may be described as a 'hardware decelerator'. The idea is to exploit spare block RAM resources to implement FSMs using fewer LUTs. The background rationale for such a technique is the availability of spare BRAMs 'for free' in Platform FPGAs. Benchmarks and two detailed case studies of the concept are presented demonstrating LUT savings of up to 90%. The technique enables greater design mapping flexibility whilst still meeting function and timing requirements.