InP-DHBT linear modulator driver with a 3-Vppd PAM-4 output swing at 90 GBaud: from enhanced transistor modelling to integrated circuit design

In this article, we report on the modelling, design and characterisation of Indium phosphide (InP) double heterojunction bipolar transistor (DHBT) devices and integrated circuits (ICs) for next generation optical communications. Critical aspects of transistors' modelling and its influence on the IC design are detailed, as well as the design and characterisation of a lumped linear modulator driver featuring a 3-Vppd PAM-4 output swing at 90 GBd. In particular, we propose an electromagnetic (EM) simulation-based parasitic extraction method of the DHBT access structures, to refine the DHBT and ICs performance prediction accuracy. It is shown to provide a better estimation of a canonical cascode gain and mu stability factor at millimeter-wave frequencies, as well as a better estimation of the driver IC gain in the 50-110 GHz frequency range. Furthermore, a high-frequency gain boosting (self-peaking) topology, based upon an emitter-degenerated paralleled-transistor cascode configuration, is analysed using a simplified transistor model, and leveraged to enhance the linear driver output-stage gainbandwidth product, with controlled amount of peaking gain. The driver IC was implemented in a 0.5-um InP-DHBT technology and features a bandwidth well in excess of 110 GHz, with 13 dB of peaking gain at 95-GHz. Besides, it achieves a 9.3-dBm single-ended output power at 1 dB of gain compression and a 2.8 percent rms-THD at a 3-Vppd output swing. The driver power consumption is 0.67 W, which is among the lowest in the state-of-the-art, and shows a 1.5-GBd driver figure-of-merit (FoM). To the best of the authors knowledge, this driver achieves the highest over-64 GBd 4-level pulse-amplitude modulation (PAM-4) performances reported to date, without digital signal processing (DSP) or postprocessing.