Limitation of spacer thickness in titanium salicide ULSI CMOS technology (I).

We have examined the gate spacer leakage in 15-20micron wide MOS devices with various thicknesses of gate spacer ranging from 25 to 100 nm. The gate oxide of all devices is 12.5 nm. Experimental results show that for the devices with only 25 nm thick of gate spacer, a broad spectrum of gate-to-source (drain) breakdown voltage, at a leakage current level of 2 microamps, is measured in the range of 1.5 to 10 volts. Using a specific tester with a total of gate spacer perimeter of 10 cm, the statistical data taken on more than 100 tester chips exhibit that, as the thickness of gate spacer is reduced to less than 50 nm, the gate leakage increases to 10 sup -9 A range at gate bias equal to 5 volts at one sigma point. A plausible explanation of this gate spacer leakage current degradation in MOS devices with thin gate spacer is the diffusion of titanium into gate spacer during salicide process, which degrades the isolation integrity and therefore generates a leakage path.