Logic Simulation Algorithms for Pipelined Hardware Architectures

In this paper, we will describe fast and accurate logic simulation algorithms that are specially suited for pipelined accelerator architectures. We will demonstrate practical approaches to partitioning the simulation algorithm in an optimal way so that no one stage in the pipeline is a bottleneck for achieving high performance. Efficient algorithms for handling special situations like, zero-delay gate evaluations, event cancellations, spike filtering, oscillation detection, etc., are described.