Model-Based design of a 5G uplink physical-layer receiver chain from UML/SysML diagrams

Future 5G networks are by design computationally challenging and demanding. These demands can only be met by utilizing mixed architectures, i.e., DSPs and FPGAs. However, utilizing these architectures in a computationally efficient manner is not trivial and design process takes huge amount of time. To overcome this bottleneck of design time we need to have unified tools capable of rapidly exploring, partitioning and prototyping the reconfigurable mixed architecture designs for 5G systems. At DATE 2017 University Booth, we demonstrate such a unified tool and show our latest achievements in the automatic code generation engine of TTool/DIPLODOCUS, a UML/SysML framework for the hardware/software co-design of data-flow systems, to support mixed architectures. Our demonstration will show the full design and evaluation of a 5G physical layer receiver for multi-core DSP and FPGA platforms. We will validate the effectiveness of our solution by comparing automated vs manual designs.