Multi-channel data-clock-recovery unit in a CMOS macrocell design

A multi-channel data-clock-recovery circuit has been implemented in 3.3 V 0.35 μm CMOS technology capable of terminating up to 24 channels at both 65 MHz and 32 MHz. The macrocell contains a manually tuned full-custom analog clock-synthesizer, a standard-cell digital clock-recovery block and testability blocks. The discussion focuses on back-end design methodology: various CAD tools utilized for simulating and integrating device-level and gate-level models, physical layout issues, verification and production-test strategy with an emphasis on design practices to support reuse and adaptability that are core concepts of a macrocell design methodology. Test chips were made to evaluate the macro which is now being used in ASICs