Packaging Issues for Integrated Circuits

A complete circuit design includes not only the circuit itself but also its environs. Many circuit designers design the chip to perform a particular function, completely ignoring where and how it will be used. One of the most overlooked aspects of circuit design is packaging. This paper will discuss the effects of packaging on circuit design. The primary functions of a package is to protect the chip from damage and to spread the terminals out to a position where they can be readily used. These functions can be achieved in many ways, such as: 1) bonding the chip directly to a FIC (Film Integrated Circuit), wire bonding it and covering the chip with RTV, 2) bonding a beam leaded chip directly to the FIC and covering it with RTV, 3) bonding the chip in a DIP (Dual Inline Package), or 4) bonding the chip in a chip carrier, to name but a few. However, each of these introduce parasitic inductance, capacitance, and resistance. Whether these parasitic elements are detrimental to the circuit performance depends on the particular circuit design.