Partitioning Circuits for a Multiprocessor-Based MOS Timing Simulator.
31 October 1986
Several strategies for partitioning circuits for a multiprocessor- based MOS timing simulator are described and evaluated. Performance of the simulator was not significantly affected by different partitioning strategies. An empirical analysis of runtime load balance amongst the processors showed that the concurrency exploitable by the multiprocessor-based simulator is limited by the dynamic nature of the load imbalance and is a function of circuit topology and input stimuli.