Performance Improvement Techniques for Synthesis

We present two new techniques that can be used in synthesis to reduce the critical path delay of the synthesized design. Results elsewhere have shown that the critical path delay is usually through the controller logic, especially when large amount of sharing is present. This paper focuses on two techniques to reduce the controller delay. In the first technique, the path delay is improved by eliminating some of the controller logic, namely, the latch signals for the flip-flops. This is done by using flip-flops with no latch control signal (hereafter called NLC flip-flops), that is, flip-flops in which data values are latched in every clock cycle. All existing synthesis algorithms we know of, use flip-flops that store data over a number of control steps. These flip-flops are latched only when a new data value is to be stored. When no-load flip-flops are used, data values have to be saved in every control step. There is no need to provide a latch signal to these flip-flops since the data values keep propagating forward in every clock cycle. In the second approach, non-encoded multiplexers are used in the data path instead of the standard encoded multiplexers (in a non-encoded multiplexer, there is a separate select line for each input).