Pull-In Range of a Phase-Locked Loop With a Binary Phase Comparator

The phase-locked loop (PLL) is an important element of many modern communication and control systems. A PLL block diagram is shown in Fig. 1. The input Vi(o>0t + is a narrow-band signal with carrier frequency w 0 and phase $i(t). This phase is compared with the phase 02{t) of the voltage-controllecl oscillator (VCO) in the phase comparator (PC). The PC output /(£), where = 0i -- 02 , is filtered f > by the loop filter II (p) and applied to the VCO control terminal. Depending on the values of the PLL parameters, the phase error 0 can be kept small even with input phase modulation. Thus with Q(t) = tit + 0io, which represents a constant input frequency offset, the system can produce a synchronized signal v2(t) with frequency 0 + D fi. This synchronization capability leads to PLL applications in carrier extraction, 1 frequency synthesis, 2 narrow-band filtering, 3 FM demodulation, 3 timing extraction in PCM and data transmission systems, 4 etc. In this paper, we examine the acquisition, or pull-in, range of a PLL with a binary PC. We present numerical results for the special case of a second-order PLL with either low-pass or phase-lag loop filter. The PC characteristic considered here is the binary curve shown in Fig. 2. It is of interest in at least three situations. First, since many synchronization systems are designed to operate with very small 22S9