Pull-In Range of a Phase-Locked Loop With a Binary Phase Comparator

The phase-locked loop (PLL) is an important element of many modern communication and control systems. A PLL block diagram is shown in Fig. 1. The input Vi(o>0t + is a narrow-band signal with carrier frequency w 0 and phase $i(t). This phase is compared with the phase 02{t) of the voltage-controllecl oscillator (VCO) in the phase comparator (PC). The PC output /( by the loop filter II (p) and applied to the VCO control terminal. Depending on the values of the PLL parameters, the phase error 0 can be kept small even with input phase modulation. Thus with Q(t) = tit + 0io, which represents a constant input frequency offset, the system can produce a synchronized signal v2(t) with frequency