SALVO - A Path to 25 nm Bulk CMOS with Optical Lithography

As silicon devices continue to scale, any alternative process and/or device architecture has to meet four critical challenges: (1) performance - I sub (on), I sub (off) and SCE have to scale favorably; (2) contact - viable contact scheme with low R sub c and R sub s for gate and S/D; (3) CMOS-NMOS and PMOS can be optimized with one process flow; and (4) compatibility - easy to make longer/wider channel devices and compatible with established processes, materials and tools. In this work, we introduce the device architecture of self-aligned local-channel V-gate with optical lithography (SALVO) with following features: (1) self-aligned local channel implants to help produce the sharp lateral channel doping profiles required to suppress SCE for 25 nm CMOS on bulk substrate[1]; (2) low R sub s S/D and gate silicided contact; (3) providing gate stack options as with other replacement gates [2,3]; (4) extending optical lithography down to 25 nm gate length with well-established spacer technique.