Synthesis of Robust Delay-Fault Testable Circuits: Theory

Correct operation of logic circuits requires propagation delays of all paths in the circuit to be smaller than a specified limit. Physical defects and processing variations in integrated circuits can affect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, highly or completely delay-fault testable circuits, one has to fully understand the sources of untestability. Ideally this requires the determination of necessary and sufficient conditions for delay-fault testability. Synthesis procedures that produce testable logic realizations by satisfying sufficient conditions for delay-fault testability can then be based on this understanding. There is often an area/performance overhead associated with these procedures, but an understanding of both the sufficiency conditions and the techniques of logic optimization can alleviate the overhead by minimally constraining the optimization to achieve full testability.