THERMAL MODELING OF A SILICON GERMANIUM (SIGE) RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) FOR WIRELESS COMMUNICATIONS

The creation, transport and storage of digital information is growing at rates of 40% to 50% annually, with video, mobile broadband, and machine-to-machine communication (Internet of Things, cloud computing, etc.) being the main drivers. The implementation of so-called fifth generation (5G) wireless networks is enabling this continued growth as well as heralding in a new era of revolutionary applications and functionality due to increases in bandwidth and reductions in communication latency. Key enablers of 5G networks include new frequency spectrum (e.g. mmWave), massive MIMO technology and new material systems. Silicon germanium (SiGe) is one such material system that offers the potential to develop Radio Frequency Integrated Circuit (RFIC) technology that can integrate many analog functions into a single integrated circuit, thereby realizing significant reductions in the overall size of a physical system, with concomitant savings in cost and power. In this article we present a modeling methodology for simulating die-level heat transfer for an RFIC comprising SiGe devices on a silicon die in a flip-chipped configuration. This is a challenging thermal problem as the form factor of the RFIC device has shrunk by over two orders of magnitude relative to its analog counterpart, leading to a proportional (100X) increase in die-level heat density that makes package-level thermal management challenging. Figure 1 shows a photograph of the die studied as part of this work, which is a transceiver designed for communication in the 27-43.5 GHz frequency range [1]. The modeling approach utilizes a combination of detailed and compact thermal models to accurately capture self-heating and heat spreading effects within the silicon die and heat flow through an array of thermal bumps located between the silicon die and the signal and ground lead frame, which is the dominant path for heat transfer from the RFIC to the environment. The die-level model groups the majority of SiGe devices into functional blocks with an associated form factor and heat dissipation profile; this approach is sufficient to estimate the local silicon die temperature, which is an important operational parameter to quantify in order to mitigate any potential electromigration effects due to high current densities, while reducing the computational complexity of the overall model. The most stressed devices on the die are then modeled in enough fine-scale detail to capture important local effects such as self-heating and thermal crosstalk between adjacent devices. The computed local silicon die temperature near the most stressed devices is then used as input to experimentally validated transistor-level thermal models accounting for self-heating, thermal crosstalk, and nonlinear thermal conductivity effects to estimate the junction temperature for the most stressed devices. The modeling methodology provides important information to characterize the thermal behavior of the SiGe RFIC, which is useful to improve the thermal design (for example, by the addition of thermal bumps in high-heat-density locations) and to ensure that the device does not exceed the manufacturer-specified Safe Operating Area (SOA) during its lifetime.