Fabrication and Performance Considerations of Charge-Transfer Dynamic Shift Registers

There has been a renewed interest recently in the use of charge storage on p-n junctions or capacitors for memory and shift register applications. 1- '' Because leakage currents gradually degrade the stored information, the memories require periodic refreshing, but the simplicity, speed, small size, and modest power requirements of many schemes and their compatibility with silicon technology can often offset the disadvantage of the regeneration requirement. This class of memories can be divided into two general groups--those which are designed for random access, and those which are inherently dynamic shift registers and can only be accessed serially. This article is particularly concerned with the dynamic shift register. Several dynamic shift registers have been proposed which use charge storage on metal-oxide semiconductor (MOS) capacitors 3-6 and at least one of these is presently available commerically. 6 Two of the most promising are the CCD first described by Boyle and Smith, 3 and the I G F E T bucket-brigade shift register reported by Sangster and Teer. 4,5 These two register schemes are similar in many respects, and we shall refer to both of them as charge-transfer shift registers. The purpose of this paper is to describe in detail the operation, fabrication, and performance of these two MOS charge-transfer shift registers, with particular emphasis on digital applications, and to bring out both their similarities and differences. In order to provide a basis for comparison, we assume 10 /tin metallization photolithographic tolerances.