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Interconnect Synthesis without Wire Tapering

01 January 2002

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Interconnect synthesis techniques such as wire sizing and buffer insertion/sizing have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works which study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice, since it is difficult to integrate into a coherent routing methodology. This work studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result which shows that wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering. Motivated by this observation, we present a general formulation for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing. We then present an optimal polynomial time algorithm that solves it. Further, we show how one can control design resource allocation within the simultaneous optimization.