Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits

Test patterns for large VLSI circuits are often determined from knowledge of the circuit function. A gate-level fault simulator is then used to find the effectiveness of the test patterns in detecting "stuck-at" faults. Existing gate levle fault simulation techniques impose prohibitively expensive performance penalties to the for modern VLSI circuits of larger sizes. Also, post-synthesis findings of such fault grading and test generation efforts are too late in the design cycle to be useful for improving the design architecture for Design-For-Test (DFT) reasons. However, due to lack of effective Register-Transfer Level (RTL) fault model, test related tasks are still performed on the gate levle netlist during post-synthesis phase of the high-level design methodology. In this paper, a unique procedure is described that enables one to perform fault simulations for a given set of test patterns and generate RTL fault coverage prior to logic synthesis.