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Statistical Device Models from Worst Case Files and Electrical Test Data

01 November 1999

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Two statistical MOS models are described, one based on worst case files and the other on electrical test data. The former is appropriate for predicting the variability of a process early in its life cycle, while the latter would better track a maturing process. The key statistical tool that is used to develop the models is principal component analysis, which is used in novel ways in order to derive statistical models from readily available information. The models are used to perform statistical circuit simulation in order to quantitatively predict the impact of manufacturing variations on circuit performance metrics. Due to the use of linear response surface modeling and latin hypercube sampling, the simulation cost of using the models is about the same as with worst case simulation. The modeling technique is general and is applicable to other semiconductor devices besides MOS devices which are considered in this paper.