The Design and Analysis of a 50Mb/s Phase-Locked-Loop Timing Recovery Circuit
01 January 1988
The design issues involved in the implementation of a monolithic, phase-locked-loop based, 50 Mega bit per second data-clock-recovery circuit are explored. Particular emphasis is placed on the qualitative factors which motivated the selection of the phase-detector, loop-filter and frequency-difference-detector used in the circuit. The results achieved with the integrated circuit designed as a result of this research are also reported. Much of the device data, along with a photomicrograph of the die appears in the IEEE International Solid-State Circuits Conference Digest of Technical Papers, Ed. 1, February 1988, in a paper entitled, "A 45MHz CMOS Phase/Frequency-Locked Loop Timing Recovery Circuit", coauthored by R.H. Leonowich and J.M. Steininger.