Topological Design and Analysis of Virtual Circuit Based LANs.

In this memorandum we formulate an optimization model for the topological design and analysis of virtual circuit based Local Area Networks (LANs). In particular, we focus on the impact of various network component constraints on network design parameters such as trunk costs, trunk utilization, and topological connectivity. The switching node constraints considered are the limit on the maximum number of circuits allowed in a node. Alternatively, these constraints can also be represented as the limit on the memory available in the switching node. The switch memory used is a function of the number and type of channels allocated in a node. The link constraints considered are the limit on the maximum number of circuits that can be routed over a link and the minimum number of circuits that must be routed over a link for the link to exist. The problem is formulated as a mixed-integer linear model. Traffic inputs to the model include the endpoint traffic matrix of circuits originating and terminating at each endpoint (switching node). It is envisioned that this model will be part of a toolkit of network design and analysis tools.