Ultrathin (<4 nm)SiO sub 2 and Si-O-N Gate Dielectric Layers for Silicon Microelectronics: Understanding the Processing, Structure and Physical and Electrical Limits

Nature has endowed the silicon microelectronics industry with a wonderful material, SiO sub 2, as shown in Table 1. SiO sub 2 is native to Si, and with it forms a low defect density interface. It also has high resistivity, excellent dielectric strength, a large band gap, and a high melting point. These properties of SiO sub 2 are in large part responsible for enabling the microelectronics revolution. Indeed, other semiconductors such as Ge or GaAs were not selected as the semiconducting material of choice, mainly due to their lack of a stable native oxide and a low defect density interface. The metal-oxide-semiconductor-field effect-transistor (MOSFET), is the building block of the integrated circuit. The Si/SiO sub 2 interface, which forms the heart of the MOSFET gate structure, is arguably the world's most economically and technologically important materials interface. The ease of fabrication of SiO sub 2 gate dielectrics, and the well passivated Si/SiO sub 2 interface that results, have made this possible. SiO sub 2 has been and continues to be the gate dielectric par excellence for the MOSFET. Figure 2 is a transmission electron photomicrograph of an actual sub-micron MOSFET, showing the SiO sub 2 gate dielectric as well as the Si/SiO sub 2 interface.