500MHz GaAs Macrocell Library for High Speed Low Power LSI Digital ASICS
16 April 1990
A library of custom macrocells has been designed for use in the DARPA III Pilot line. These cells are designed to provide maximum performance and LSI functionality while minimizing the power requirements. The entire library may be clocked up to 500 MHz with smaller cells, such as flip-flops, sustaining closk rates up to 2 GHz. The macrocells are designed around a SFFL logic family which uses a 2.0 volt power supply. Inputs and outputs are designed to drive 50 OMEGA transmission lines with a 1.0 volt swing.