The challenge of testing silicon integrated circuits (iCs) is becoming more formidable with the rapidly expanding production of large-scale integrated (LSI) circuits.
This paper describes fault simulation algorithms for the MARS hardware accelerator designed and developed at the AT&T Bell Laboratories. Two algorithms are considered.
The paper discusses the issues involved in providing an integrated fault-tolerance solution to enterprise applications with distributed three-tier architecture.
2235 Therefore, we have attempted to extend the existing methods, wherever necessary, before making the comparisons between methods.
A class of multipath multistage interconnection networks (MINs) is presented in this paper. These MINs can be designed to have the degree of fault-tolerance desired.
A class of multipath multistage interconnection networks (MINs) is presented in this paper. These MINs can be designed to have the degree of fault-tolerance desired.
The recovery and repair durations of large fault-tolerant systems gen-erally span several orders of magnitude.
A class of multipath multistage interconnection networks (MINs) is presented in this paper. These MINs can be designed to have the degree of fault-tolerance desired.
A message trunk, the basic connecting link in the switched telephone network, provides the communication path between switching machines as well as certain call setup capabilities, such as supervis
Scattering with angular limitation projection electron-beam lithography promises significant cost benefits over optical lithography for features down to 35nm.
