A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications.
We propose and validate a bandwidth-limited RSOA based 100Gb/s TWDM-PON scheme with centralized wavelength generation technique and duplex equalization of 12.5Gb/s NRZ optical signals carried on 8
We demonstrate a DWDM-TDMA PON with symmetric 320Gb/s capacity shared between 16384 customers.
The symmetric band Lanczos process is an extension of the classical Lanczos algorithm for symmetric matrices and single starting vectors to multiple starting vectors.
A CMOS process is described that is designed to optimize the transistor characteristics of both the n-channel and p-channel devices simultaneously.
A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously.
We describe the design, implementation, and experimental evaluation of a clock recovery algorithm suitable for synchronization over a packet-based metro-area network (MAN) using the protocol based
Finite state concurrent systems arise in many applications. Both sequential circuits and communication protocols can be viewed as implementing such systems at some level of abstraction.
This paper describes work under progress on synthetic visual environments.
