B.S.T.J. Briefs: A Josephson Parallel Multiplier

A Josephson Parallel Multiplier By T. A. FULTON and L. N. DUNKLEBERGER (Manuscript received January 14, 1982) This report describes the operation of an 8- x 12-bit parallel multiplier which employs Josephson tunnel junctions (Fig. I). 1 * The device contains 548 junctions used in two-junction "Jaws"-type logic elements.2 Ninety-six of these logic elements function as A N D gates to form the partial products. Their outputs are fed into a Wallace-tree3 arrangement of 89 full adders, each having one Jaws for the C A R R Y computation and one for the SUM. The thirteen most significant bits of the product are returned to the outputs. A latching-logic mode of operation is used.1 This employs a fivephase ac current supply for power and timing, provided by unipolar pulses from a room-temperature word generator. The minimum cycle time achieved is 75 ns, with a latency time delay between input and output of 30 ns measured at the room-temperature connectors. Both times are within design specifications. The latency time is determined primarily by the time required for settling of the power-supply pulse amplitudes (20 ns total) and by the round-trip cable delay (8 ns) from the room-temperature connectors to the chip immersed in liquid He. The worst-case logic delay for the Jaws elements (ripple carry through 18 stages) is estimated as