B.S.T.J. Briefs: Serial Coding for Cyclic Block Codes

In 1972 the concept of serial encoding and decoding for single error correcting BCH codes was introduced.1,2 In this note, the concept of serial encoding and decoding is generalized and the timing diagrams are presented for a typical (n, k) cyclic block code. The implementation in conventional technology uses only one exclusive-OR gate and is presented for all (n -- k) order generator polynomials for any code n bits long. The implementations presented are valid for all cyclic block encoders and for all decoders with single error correction with multiple error detection capability. Most of the literature 3 4 on encoders and decoders emphasizes the binary division process between the data polynomial d(X), k bits long, and the generator polynomial g(X), p bits long, in conventional BCH type of error correction. In general, the division is accomplished by distributing a series of exclusive-OR gates embedded in a shift register. The associated logical functions to be accomplished to maintain synchronism between bits of the code word c(X) at the encoder and the corresponding synchronizing logic at the decoder are both ignored. With the recent advent of high-speed logic circuitry, it appears redundant to use a large number of exclusive-OR gates and unduly complicate the logic involved. Instead, a single exclusive-OR gate* may be used in the serial coding where the contents of the shift register in the encoders and decoders are completely circulated once for each step * The principle of performing serial encoding by using a single exclusive-OR gate has been described in Refs.